1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a configuration of a data bus of a semiconductor memory device for allowing flexible alteration of an input/output data bit width. More particularly, the present invention relates to a configuration for carrying out a multi-bit test of compressing (degenerating) memory cell data of a plurality of bits to one-bit data.
2. Description of the Background Art
In a data processing system, the bit width of data transferred between a processor and a semiconductor memory varies according to a processor used. In order to achieve high data transfer speed and high processing speed, it is preferable that the bit width of transfer data is wide. In a semiconductor memory device, however, there is a restriction of a pitch condition of a pin terminal. Therefore, from the viewpoint of reduction in size of a package and the like, the upper limit exists in the data bit width.
It may be considered to dispose a plurality of semiconductor memory devices in parallel for use as a so-called module to widen the bit width of transfer. In this case, however, the scale of the system becomes large to be against the trend of down-sizing of the whole system.
In order to solve the problems as described above, with recent improvements in microfabrication technology, increase in memory capacity and miniaturization of a semiconductor memory device and reduction in pin terminal, a semiconductor memory device capable of inputting/outputting multi-bit data is being implemented. However, different systems to which the semiconductor memory device is applied have different bit widths of transfer data, and the semiconductor memory device is also required to maintain the compatibility with the previous generation. Thus, a semiconductor memory device having a plurality of kinds of bit widths of input/output data is fabricated on a common chip.
Specifically, when fabricating semiconductor memory devices having various bit widths of input/output data individually, since the internal configuration is the same irrespective of the data bit widths and only the data bit width of input/output data varies, the designing efficiency deteriorates and management of products also becomes complicated.
Generally, a semiconductor memory device is fabricated commonly to a plurality of kinds of data bit widths, and a data bit width is set by mask interconnection in slicing or by bonding option fixing a specific bonding pad at a predetermined voltage. The fabrication process can be made common for semiconductor memory devices of a plurality of kinds of data bit widths, common design can be used to design internal circuitry commonly to a plurality of kinds of input/output data bit widths. Thus, the design efficiency is improved.
In the case where a common semiconductor memory device is used for a plurality of kinds of data bit widths, the internal configuration is the same, and only an input/output circuit to be used is different for a different input/output data bit width. According to a data bit width to be used, connection between an internal data line and an input/output line is changed. In the case of connecting an internal data line to different input/output lines according to the data bit width to be used, the configuration for switching the connection of the internal data lines becomes complicated, and an internal interconnection is also made complicated.
When the correspondence relation between a write/read circuit for generating internal write/read data and an input/output circuit or connection between the write/read circuit and an internal data line is changed according to the data bit width to be used, switching of connection of an internal data line becomes complicated. The write/read circuit includes a preamplifier for amplifying read data from a memory cell and generating internal read data, and a write driver for generating data to a memory cell in accordance with internal data from a write data inputting circuit.
To assure reliability of a semiconductor memory device, a function test to determine whether data is accurately written/read is performed. Such function tests includes a multi-bit test in which a plurality of memory cells are tested simultaneously. Common data is first written into a plurality of memory cells, then data read from the plurality of memory cells is compressed to data of one bit, and the one-bit data is output. In such a multi-bit test, a plurality of memory cells are tested at a time, so that the test time can be shortened.
However, in the case of the configuration for adapting to a plurality of kinds of data bit widths, it is required to perform the multi-bit test according to the data bit width to be used. In addition, in the case of changing the connection of an internal bus in accordance with a data bit width to be used, in order to maintain the pattern of test data for memory cells, the positional relation between the memory cells of compression target has to be maintained for the plurality of output/output data bit widths. Specifically, the same test pattern has to be written into memory cells in each respective data bit width. It is necessary to perform writing of common data, data reading and compression on memory cells in a predetermined positional relation. In the case of changing the connection of an internal data line in accordance with the data bit width, if the connection of the compression circuit is also switched, the configuration of the compression circuit is made complicated due to implementation of switching the connection, and the circuit occupying area increases.
Irrespective of the data bit width to be used, the test contents to be performed are the same. It is therefore desirable to use a common tester. Consequently, compressed data has to be output to the same terminal/pad irrespective of the data bit width to be used. In the case of changing a path for transferring output data of the compression circuit in accordance with the data bit width to be used, a circuit for changing the path for transferring output data of the compression circuit in accordance with the data bit width used is required to increase the circuit occupying area. In addition, the switching circuit is connected to a bus used in the normal operation mode, and the load associated with the bus increases.
To write/read test data, it is preferable to use the common test data terminals for writing/reading test data irrespective of the data bit width to be used, so that a common tester can be used for the plurality of kinds of data bit widths of the semiconductor memory device.
An object of the invention is to provide a semiconductor memory device capable of implementing a plurality of data bit widths without greatly changing the internal configuration.
Another object of the invention is to provide a semiconductor memory device having a plurality of kinds of data bit widths, on which a multi-bit test can be easily performed.
Further another object of the invention is to provide a semiconductor memory device on which a multi-bit test can be performed using a common tester for a plurality of data bit widths without greatly changing an internal configuration.
A semiconductor memory device according to the invention includes first data terminals of a first bit width used in both a mode of a first data bit width and a mode of a second data bit width wider than the first bit width, and a first main data line of the first bit width disposed corresponding to the first data terminals. The correspondence relation between the first main data line and the first data terminals is the same in both the mode of the first bit width and the mode of the second bit width.
The semiconductor memory device according to the invention further includes a second data terminal that is not used in the mode of the first bit width, and a second main data line disposed corresponding to the second data terminal and has a bit width equal to that of the second data terminal. The second data terminal has a bit width equal to the difference between the first and second bit widths.
By disposing the second main data line used exclusively in the mode of the second data bit width, the same correspondence relationship between the first main data line and the data terminal can be made the same for both modes of the first and second data bit widths. Thus, the modes of the first and second bit widths can be accommodated for without changing the internal bus arrangement.
Since there is no change in the corresponding relationship between the internal bus and the input/output circuit, when internal data bits are compressed, it is sufficient to compress only data of the same main data line in the modes of both the first and second bit widths. Thus, the configuration of the compression circuit can be simplified.
In switching of the bit width, the switch of the connection between the first main data line and the memory block can be minimized to minimize the change in the configuration in association with the change in the bit width, and a change in the bit width can be easily accommodated for.
Data indicative of the compression result can be easily output to the same data terminal in both of the modes of the first and second bit widths, and a test can be performed using the common tester irrespective of the data bit width.
In the mode of the first bit width and the mode of the second bit width, the unit number of data bits to be compressed can be changed. The same data terminal can be used for outputting the compression result, and a test can be performed using the common tester.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.